Semiconductor Device with of Modulating Gain Coefficient and Semiconductor Integrated Circuit Including the Same
1. Field of the Invention
The present invention relates to a device structure that relieves a limit of miniaturization due to physical constraints of the device structure in a semiconductor integrated circuit (e.g. LSI: Large Scale Integrated circuit), and a configuration of a semiconductor integrated circuit having the device as a component.
2. Description of the Background Art
Semiconductor integrated circuits represented by LSI have improved in performance, i.e., increase in integration and speed, and reduction in power consumption, by mainly miniaturizing devices for over thirty years since its manufacturing technology was established.
In these days when a minimum wiring width indicating the level of device miniaturization have reached 0.15 xcexcm, however, various constraints due to physical phenomenon have become obvious in the device miniaturization. The minimum wiring width generally corresponds to a gate length L of a transistor. Such constraints makes it difficult to further miniaturize devices by the conventional technique, meaning that improvement in LSI performance by the device miniaturization can no longer be expected in the conventional trend.
First, the outline and future problems of the conventional miniaturization technique of semiconductor devices will be described. FIG. 26 schematically shows an example in which a device is miniaturized according to a constant electric-field scaling law, the most popular rule for MOS (Metal Oxide Semiconductor) transistors.
FIG. 26 (b) illustrates an MOS transistor which is reduced to a scale of one-half of the device shown in FIG. 26 (a). Important parameters for determining the characteristic of the MOS transistor includes, as shown in FIG. 26 (a), a gate length L, a gate width W, a thickness of an insulation film (a thickness of a gate oxide film) TOX, a diffusion depth of source and drain Xj, a concentration of impurities introduced at a substrate or a channel portion directory below the gate, and a power-supply voltage Vd.
A scaling law for these parameters is, as indicated in the middle column in Table 3, the constant electric-field scaling law where L, W, TOX, Xj and Vd, are reduced by an inverse of a scaling parameter xcex1 and only N is multiplied by xcex1.
According to the constant electric-field scaling law, the magnitude of the electric field is constant irrespective of size reduction of the device. MOS transistors and the like have a constraint in that the electric field within the device (in particular, in the drain or the like) cannot be increased to prevent hot carriers from increasing in order to ensure reliability.
As a physical phenomenon, however, current starts to flow between the substrate (or the channel portion directly below the gate) and a gate electrode when thickness of insulation film (thickness of gate oxide film) TOX becomes thinner than approximately 3 nm. Thus, the thickness of the gate oxide film cannot be made thinner than approximately 3 nm because of the physical constraint of tunnel current. Thickness of insulation film (thickness of gate oxide film) TOX of 3 nm corresponds with gate length L of approximately 0.12 xcexcm.
If gate length L is approximately 0.12 xcexcm or shorter, miniaturization must be performed according to an irregular constant electric-field scaling law in which only thickness of insulation film (thickness of gate oxide film) TOX is constant, as indicated in the rightmost column in Table 3. Moreover, it is required for an MOS transistor to suppress its short channel effect in order to accurately operate as a switch device. For that purpose, diffusion depth Xj of the source and drain must be reduced by a factor of 1/xcex1, while the concentration of introduced impurities must be increased so as to lower the electric resistance, in order to prevent deterioration of drivability of the source and drain. Furthermore, because the source and drain are formed by diffusion, it had gradually been difficult to reduce diffusion depth Xj at a rate of 1/xcex1 if diffusion depth Xj becomes smaller than several tens of nm.
In recent years, therefore, effective reduction of diffusion depth Xj (i.e. suppress of the short channel effect) has been expected by a so-called fully-depleted SOI (Silicon On Insulator) device in which an Si thin film is formed on an insulation film and a transistor is formed thereon. For practical application of the SOI device, however, a backstage effect, a substrate potential floating, a parasitic bipolar effect and the like must be newly addressed, leaving some technical issues to be solved.
Here, assuming that diffusion depth Xj can be effectively reduced at a rate of 1/xcex1 by e.g. the fully-depleted SOI device, and that the irregular constantelectic-filed scaling down can be performed where only thickness of insulation film (thickness of gate oxide film) TOX is constant when gate length L is 0.12 xcexcm or shorter, the trend of the LSI performance is estimated in the device miniaturization. FIG. 27 shows a conventional trend of device miniaturization, with consideration given to the physical constraints for thickness of insulation film (thickness of gate oxide film) TOX.
Referring to FIG. 27, it is assumed that COX is a gate capacitance which is inversely proportional to thickness of insulation film (thickness of gate oxide film) TOX, and that a dielectric constant xcex5 of the insulation film is constant. Since the drivability of the device is proportional to gate capacitance COX, improvement in performance can be expected by multiplying dielectric constant xcex5 of the insulation film by xcex1 even if thickness of insulation film (thickness of gate oxide film) TOX is constant. To change dielectric constant xcex5 of the insulation film, however, the material for the insulation film must be changed, which appears to be difficult in practical application.
Table 4 shows a scaling law for wiring. In order to improve the LSI performance, reduction in the area of wiring that is proportional to the area reduction of the device must be realized for a higher degree of integration. As to increase in operation speed and reduction in power consumption, a wiring capacitance must be reduced. The wiring had conventionally been scaled down without a change of a wiring material (e.g. Al), i.e., with constant electric conductivity "sgr". Recently, however, a material such as Cu (copper) is introduced in an attempt to increase electrical conductivity "sgr" in order to avoid a revealed wiring delay, i.e., the wiring capacitance being larger with respect to a device capacitance such as a gate capacitance, hindering improvement in the LSI performance. Moreover, a method of making the thickness of wiring or interlayer film larger than that in the scaling rule has been considered. In any case, in the scaling law of wiring, the wiring capacitance that greatly affects a signal delay is expected to be reduced by a factor of 1/xcex1, as indicated in Table 4.
As to the device and wiring, according to the scaling laws indicated in Tables 3 and 4, effects can be expected for the parameters related to the LSI performance (area A, signal delay time T, power consumption P) indicated in Table 5. Here, because the area is proportional to an inverse of the degree of integration and the signal delay time is proportional to an inverse of operation speed, reduction of either one of the above results in higher performance.
In the leftmost column in Table 5, the relation between the performance parameter and various parameters are indicated. It should be noted that a capacitance C that affects the operation speed and the power consumption is reduced to 1/xcex1.
Though device capacitance alone is rapidly reduced by a factor of 1/xcex12, the wiring capacitance is reduced by a factor of 1/xcex1 so that capacitance C which is the sum of the device capacitance and the wiring capacitance is also reduced to 1/xcex1. At first, the fully-depleted SOI device was expected to have higher performance by reducing its device capacitance. In terms of the LSI miniaturization, however, capacitance C is controlled by the wiring capacitance and is reduced as miniaturization proceeds, producing little effect at the LSI level by the reduction of the device capacitance itself.
As can clearly be seen from Table 5, according to the constant electric-field scaling law applied to the case where gate length L is longer than 0.12 xcexcm, drain current Ids corresponding to the drivability is reduced to 1/xcex1, and both capacitance C and power-supply voltage Vd are reduced to 1/xcex1, so that signal delay time T is also reduced to 1/xcex1, realizing increased speed. When the irregular constant electric-field scaling law applied to the case where gate length L is 0.12 xcexcm or shorter and only thickness of insulation film (thickness of gate oxide film) TOX is constant, however, drain current Ids is reduced to 1/xcex12, resulting in constant signal delay time T, hindering increase of the speed.
The difference in the effects of device reduction for the signal delay speed between the constant electric-field scaling law applied to gate length L of a value higher than 0.12 xcexcm and the irregular constant electric-field scaling law applied to gate length L of 0.12 xcexcm or shorter in which only thickness of insulation film (thickness of gate oxide film) TOX is constant will be described with reference to FIGS. 28 and 30.
FIG. 28 shows the relationship between source-drain voltage Vds and source-drain current Ids in an MOS transistor. FIG. 28 also shows a gain coefficient xcex2 of the transistor. The power-supply voltage and gain coefficient before scaling-down are set as Vd0 and xcex20 respectively, whereas the power-supply voltage and gain coefficient after scaling-down are set as Vda and xcex2a respectively. In order for the transistor to accurately operate as a switch device, source-drain current Ids must be prevented from flowing when gate voltage Vg is 0V in nMOS (Vd in pMOS), i.e., when the transistor is in an OFF state, requiring the power-supply voltage to be set as Vd0, which is the voltage before source-drain current Ids starts to flow. Gate length L is reduced to 1/xcex1 after the device is scaled down, so that the power-supply voltage at gate voltage Vg of 0V is also reduced to be Vda.
The reduction in the power-supply voltage is also essential to suppression of hot carriers. As shown at an upper part of FIG. 28, assuming that mobility xcexc of carriers and dielectric constant xcex5 of the gate insulation film are constant, gain coefficient xcex2 is proportional to gate width W and inversely proportional to gate length L and thickness of insulation film (thickness of gate oxide film) Tox.
Thus, the gain coefficient after scaling-down is xcex2a, xcex1 times xcex2, in the case of the constant electric-field scaling law applied to gate length L longer than 0.12 xcexcm, whereas the gain coefficient after scaling-down is constant xcex20, in the case of the irregular constant electric-field scaling law in which only thickness of insulation film (thickness of gate oxide film) TOX is constant. Accordingly, a load that must be driven by the transistor in each case (power-supply voltagexc3x97load capacitance) and drivability (an integral with respect to source-drain voltage Vds of source-drain current Ids) are shown in FIGS. 29 and 30 where changes associated with the device reduction are schematically illustrated as areas. The drivability is herein represented by an integral with respect to source-drain voltage Vds of source-drain current Ids because it is assumed that the voltage change in the load is linear with respect to time. It is noted that, though the voltage change in the load is non-linear in practice, assumption that it is linear will not cause a great problem in macroscopic comparison of characteristics.
In the case with the constant electric-field scaling law shown in FIG. 29 for gate length L longer than 0.12 xcexcm, it can be seen that the drivability is more increased by the area ratio with respect to the load, as the device is reduced. On the other hand, in the case with the irregular constant electric-field scaling law shown in FIG. 30 in which only thickness of insulation film (thickness of gate oxide film) TOX is constant, it can be seen that the area ratio of the load and the drivability is almost constant as the device is reduced, so that no increase in speed can be expected.
In sum, expected LSI performance according to the conventional scaling law with consideration given to the above-described physical constraint, i.e. suppression of tunnel current of the gate oxide film, exhibits the trend shown in FIG. 31. These results show that, if gate length L is 0.12 xcexcm or shorter and thus the irregular constant electric-filed scaling law is applied in which only thickness of insulation film (thickness of gate oxide film) TOX is constant, drain current Ids is reduced to 1/xcex12 making signal delay time T constant, thereby hindering increase in the speed. Moreover, various difficulties for suppressing the short-channel effect still remain in the device reduction.
An object of the present invention is to enable further miniaturization of a device exceeding the limit for miniaturization in the conventional device structure, and to realize further improvement in the performance of a semiconductor integrated circuit (LSI) associated therewith.
According to an aspect of the present invention, a semiconductor device includes a source and a drain formed at respective impurity diffusion regions, a gate formed at a region between the source and the drain with an insulation film interposed, and a structure for modulating a gain coefficient xcex2 in accordance with a magnitude of a voltage between the source and the drain.
According to another aspect of the present invention, a semiconductor integrated circuit device includes a semiconductor device including a source and a drain formed at respective impurity diffusion regions, a gate formed at a region between the source and the drain with an insulation film interposed, and a structure for modulating a gain coefficient xcex2 in accordance with a magnitude of a voltage between the source and the drain.
According to a further aspect of the present invention, a semiconductor device includes a source and a drain formed at respective impurity diffusion regions, a gate formed at a region between the source and the drain with an insulation film interposed, and a structure for modulating a gain coefficient xcex2 in accordance with a magnitude of a voltage of the gate.
According to yet another aspect of the present invention, a semiconductor integrated circuit includes a semiconductor device including a source and a drain formed at respective impurity diffusion regions, a gate formed at a region between the source and the drain with an insulation film interposed, and a structure for modulating a gain coefficient in accordance with a magnitude of a voltage of the gate.
According to the present invention, therefore, the bottleneck of miniaturization due to physical constraints in the conventional MOS device can be overcome, and thus device miniaturization can relatively easily be realized in structure. This can extensively contribute to a wide range of LSI in terms of increase in integration and speed, reduction in power consumption and the like.
Furthermore, the configuration that modulates the gain coefficient xcex2 in correspondence to the magnitude of the gate voltage can realize a characteristic of a high withstand voltage and a high gain coefficient during the ON state of the transistor, though the application thereof is limited to a CMOS logic circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.